Add the arm64 NEON implementation of the ScaleInvariantMatrixMatch kernels - #1602

Add a TestInfra for the four kernel functions (compute_scale and
compute_error, plain and weighted). Each test generates a random
width x height matrix pair (and weight matrix for the weighted
variants), runs the Default path and the ISA path on identical
input, and compares the results.

The Default path is the source of truth, so each ISA registers the
same (width, height, use_weights) combinations against Default.
The sizes cover 1x1 up to 1000x1000, both divisible and
undivisible by the vector lengths (4, 8, 16), including the
short-row cases that exercise unaligned row prefixes and partial
vector tails. The SSE4.1 path back-reads up to 3 floats before a
row start, so the matrices are allocated with 16 floats of head
padding to keep those reads in-bounds.

Scales are not computed exactly by all paths (different addition
orders), so results are compared with a tolerance: pass if within
4096 ULPs, or within 1e-4 of the magnitude of the accumulated sum
(the absolute part covers near-zero results, where ULPs are far
smaller than the accumulated rounding of a multi-million-term sum).

The tests are registered per-ISA in each x86 Core file (SSE,
AVX2, AVX512), guarded by the same PA_AutoDispatch and
CPU_CAPABILITY_CURRENT checks the dispatchers use, so each
architecture only runs the tests for the ISAs it can execute.

Each ISA kernel requires a minimum row width (4 for SSE4.1, 8 for
AVX2, 16 for AVX512): below it, the partial-row loads span past the
row end and can read past the end of the allocation. The test
registration now skips sizes below the ISA's minimum width.

The test matrices also get 15 floats of tail padding after the last
row: the SSE4.1 partial-tail load (PSHUFB-based) reads a full 16-byte
word that extends up to VL - 1 floats past the row end, which would
otherwise run past the allocation on the last row.